/*
 * Bonito Register Map 
 * Copyright (c) 1999 Algorithmics Ltd
 *
 * Algorithmics gives permission for anyone to use and modify this file
 * without any obligation or license condition except that you retain
 * this copyright message in any source redistribution in whole or part.
 *
 * Updated copies of this and other files can be found at
 * ftp://ftp.algor.co.uk/pub/bonito/
 * 
 * Users of the Bonito controller are warmly recommended to contribute
 * any useful changes back to Algorithmics (mail to
 * bonito@algor.co.uk).
 */

/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */

#ifndef _BONITO_H_
#define _BONITO_H_


#define BONITO(x)	*(volatile UINTN*)((0xbfe00000)+(x))


/*********************************************************************/
/*PCI map	                                                     */
/*********************************************************************/

/* To make address spaces alike with x86 system, we put sdram
 * start address at 0 and pci devices' start address at 0x14000000 for
 * both CPU address space & PCI memory address space.
 *
 * We have 3 64M window in CPU address space to access PCI memory, for
 * convenience, these window's cpu address fall in 0x10000000 - 0x1c000000. We
 * allocate PCI device memory from 0x10000000 to make cpu address == pci
 * address to help driver writers. But to initialize VGA, we have to get access
 * pci memory at 0xc0000, and we choose to reserve the first window for this
 * purpose. Only the last two are used for pci devices. 
 * --zfx 060716
 *
 * The above scheme has a problem: two windows for pci devices are not enough.
 * Without rom the VGA chip will ask for a 128M memory space and use up all available
 * space! now we have a workaround: make the three window of sizes 128/32/32MB instead of
 * 64MB each, then use the first 128 + 32 for normal pci memory, the last 32MB to access
 * pci memory 0xc0000.
 */

#define PCI_LOCAL_MEM_PCI_BASE		0x80000000
#define PCI_MEM_SPACE_PCI_BASE		0x00000000
#define PCI_IO_SPACE_BASE		0x00000000
#define BONITO_PCILO_BASE_VA    0xb0000000
#define BONITO_PCILO_SIZE		0x0c000000
#define BONITO_PCIIO_BASE_VA		0xbfd00000
#define BONITO_PCIIO_SIZE		0x00010000
#define BONITO_PCICFG_BASE		0x1fe80000

/* Bonito Register Bases */

#define BONITO_PCICONFIGBASE		0x00
#define BONITO_REGBASE			0x100


/* PCI Configuration  Registers */

#define BONITO_PCI_REG(x)               BONITO(BONITO_PCICONFIGBASE + (x))
#define BONITO_PCICMD			BONITO_PCI_REG(0x04)
#define BONITO_PCIBASE0 		BONITO_PCI_REG(0x10)
#define BONITO_PCIBASE1 		BONITO_PCI_REG(0x14)
#define BONITO_PCIBASE2 		BONITO_PCI_REG(0x18)
/* 4. PCI address map control */

#define BONITO_PCIMAP			BONITO(BONITO_REGBASE + 0x10)
#define BONITO_PCIMEMBASECFG	BONITO(BONITO_REGBASE + 0x14)
#define BONITO_PCIMAP_CFG		BONITO(BONITO_REGBASE + 0x18)

/* pcimap */

#define BONITO_PCIMAP_PCIMAP_LO0	0x0000003f
#define BONITO_PCIMAP_PCIMAP_2		0x00040000
#define BONITO_PCIMAP_WIN(WIN,ADDR)	((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
#endif /* _BONITO_H_ */
